Publications

Conference Papers

Memory-based computing for energy-efficient AI: Grand challenges (VLSI-SoC)
Foroozan Karimzadeh, Mohsen Imani, Bahar Asgari, Ningyuan Cao, Yingyen Lin, and Yan Fang
LCP: A Low-Communication Parallelization Method for Fast Neural Network Inference for IoT (CSCE-ICOMP)
Ramyad Hadidi, Jiashen Cao, Younmin Bae, Da Eun Shim, Hyojong Kim, Bahar Asgari, Sung-Kyu Lim, Michael S. Ryoo, and Hyesoon Kim
Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge (IEEE EDGE)
Dheeraj Ramchandani, Bahar Asgari, and Hyesoon Kim
Creating Robust Deep Neural Networks With Coded Distributed Computing for IoT (IEEE EDGE)
Ramyad Hadidi, Jiashen Cao, Bahar Asgari, and Hyesoon Kim
Context-Aware Task Handling in Resource-Constrained Robots with Virtualization (IEEE EDGE)
Ramyad Hadidi, Nima Shoghi, Bahar Asgari, and Hyesoon Kim

Maia: Matrix Inversion Acceleration Near Memory (FPL)
Bahar Asgari, Dheeraj Ramchandani, Amaan Marfatia, and Hyesoon Kim

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads (IISWC)
Bahar Asgari, Ramyad Hadidi, Joshua Dierberger, Charlotte Steinichen, Amaan Marfatia, Hyesoon Kim
Best Paper Nominee!
FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction (HPCA)
Bahar Asgari, Ramyad Hadidi, Jiashen Cao, Da Eun Shim, Sung-Kyu Lim, Hyesoon Kim
Quantifying the Design-Space Tradeoffs in Autonomous Drones (ASPLOS)
Ramyad Hadidi, Bahar Asgari, Sam Jijina, Adriana Amyette, Nima Shoghi, Hyesoon Kim
Context-Aware Task Handling in Resource-Constrained Robots with Virtualized Execution (DAC)
Ramyad Hadidi, Bahar Asgari, Nima Shoghi, Hyesoon Kim

ALRESCHA: A Light-Weight Reconfigurable Sparse-Computation Accelerator (HPCA)
Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili
PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra (DAC)
Bahar Asgari, Ramyad Hadidi, Nima Shoghi, Hyesoon Kim
MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture (ICCD)
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim
ASCELLA: Accelerating Sparse Problems by Enabling Stream Accesses to Memory (DATE)
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim
Proposing a Fast and Scalable Systolic Array for Matrix Multiplication (FCCM)
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim

Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices (IISWC)
Ramyad Hadidi, Jiashen Cao, Yilun Xie, Bahar Asgari, Tushar Krishna, Hyesoon Kim Best Paper Nominee!
LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays (DAC)
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM (DSN)
Prashant Nair, Bahar Asgari, Moinuddin Qureshi
Vortex RISC-V GPGPU system: Extending the ISA, Synthesizing the Microarchitecture, and Modeling the Software Stack (CARRV)
Fares Elsabbagh, Bahar Asgari, Hyesoon Kim and Sudhakar Yalamanchili
Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs (FPL)
Younmin Bae, Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Hyesoon Kim

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube (ISPASS)
Bahar Asgari, Jeffrey Young, Burhan Ahmad Mudassar, Kartikay Garg, Tushar Krishna, Hyesoon Kim

Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube (IISWC)
Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, and Hyesoon Kim

MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System
Bahar Asgari, Saibal Mukhopadhyay, and Sudhakar Yalamanchili
Springer Journal of Signal Processing Systems, Special Issue on Embedded Machine Learning (2020)
ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
IEEE Micro, Special Issue on Machine Learning Acceleration (2019)
A Micro-Architectural Approach to Efficient Employment of STTRAM Cells in Microprocessors Register File
Bahar Asgari, Mahdi Fazeli, Ahmad Patooghy, and Seyed Vahid Azhari
IET Computers and Digital Techniques (2016)
Single Event Multiple Upset-Tolerant SRAM Cell Designs for Nano-scale CMOS Technology
Ramin Rajaei, Bahar Asgari, Mahmoud Tabandeh, Mahdi Fazeli
Turkish Journal of Electrical Engineering & Computer Sciences (2016)
Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies
Ramin Rajaei, Bahar Asgari, Mahmoud Tabandeh, and Mahdi Fazeli
IEEE Transactions on Device and Materials Reliability (2015)