Publications

2026

• Arcalís: Accelerating Remote Procedure Calls Using a Líghtweight Near-Cache Solution (MICRO) [pdf]
  Johnson Umeike, Pongstorn Maidee, and Bahar Asgari

• Sāmaya: Safe Memory Accesses to Expand Coarse-Grain Reconfigurable Array Adoption (IEEE CAL) [paper]
  Alex Coppens, Jeremy Sha, Milijana Surbatovich, and Bahar Asgari

• Márohu: Scalable CGRA Mapping through Reinforcement Learning a Hierarchical Pointer Network (Y'arch at ISCA)
  Alex Coppens and Bahar Asgari

• Orion: Online Reduction of Activation Dispatch Overhead in Disaggregated MoE Inference (MLArchSys at ISCA) [paper]
  Johnson Umeike and Bahar Asgari

• Towards Transparent and Reproducible Accelerator Research (OSCAR at ISCA) [slides]
  Ubaid Bakhtiar and Bahar Asgari

• Polaris: Enabling PIM-Optimized Low-Energy SpGEMM using a Remote-Access-Aware Mapping Solution (DAC LBR) [paper]
  Helya Hosseini, Christina Giannoula, and Bahar Asgari

• Xami: Expert-Aware Adaptive Compression for Mixture-of-Experts on Sparse Tensor Cores (IEEE CAL) [paper]
  Johnson Umeike and Bahar Asgari

• Procyon: Promoting Fine-Grained Multi-Tenancy to Optimize Sparse Streaming Accelerators (DAC) [paper]
  Ubaid Bakhtiar, Jeremy Xu Sha, Helya Hosseini, Bahar Asgari

• Situla: Studying the Interplay of Sparse Formats and CPU/GPU Libraries (ISPASS) [paper]
  Amirmahdi Namjoo, Sanjali Yadav, Helya Hosseini, Bahar Asgari

2025

• Mustafar: Promoting Unstructured Sparsity for KV Cache Pruning in LLM Inference (NeurIPS) [paper] [slides]
  Donghyeon Joo, Helya Hosseini, Ramyad Hadidi, Bahar Asgari

• Belenos: Bottleneck Evaluation to Link Biomechanics to Novel Computing Optimizations (IISWC) [paper]
  Hana Chitsaz, Johnson Umeike, Amirmahdi Namjoo, Babak N. Safa, and Bahar Asgari

• Boötes: Boosting the Efficiency of Sparse Accelerators Using Spectral Clustering (MICRO) [paper]
  Sanjali Yadav and Bahar Asgari

• Chasoň: Supporting Cross-HBM Channel Data Migration to Enable Efficient Sparse Algebraic Acceleration (MICRO) [paper]
  Ubaid Bakhtiar, Amirmahdi Namjoo, and Bahar Asgari

• Coruscant: Co-Designing GPU Kernel and Sparse Tensor Core to Advocate Unstructured Sparsity in Efficient LLM Inference (MICRO) [paper] [slides]
  Donghyeon Joo, Helia Hosseini, Ramyad Hadidi, and Bahar Asgari

• Misam: Machine Learning–Assisted Dataflow Selection in Accelerators for Sparse Matrix Multiplication (MICRO) [paper]
  Sanjali Yadav, Amirmahdi Namjoo, and Bahar Asgari

• DynaFlow: An ML Framework for Dynamic Dataflow Selection in SpGEMM accelerators (IEEE CAL) [paper]
  Sanjali Yadav, and Bahar Asgari

• Segin: Synergistically Enabling Fine-Grained Multi-Tenant and Resource Optimized SpMV (IEEE CAL) [paper]
  Helia Hosseini, Ubaid Bakhtiar, Donghyeon Joo, and Bahar Asgari

• La Superba: Leveraging a Self-Comparison Method to Understand the Performance Benefits of Sparse Accelerator Optimizations (ISPASS) [paper]
  Nebil Ozer, Gregory Kollmer, Ramyad Hadidi, and Bahar Asgari

• Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix Algebra (DAC) [paper]
  Ubaid Bakhtiar, Donghyeon Joo, and Bahar Asgari

2024

• Electra: Eliminating the Ineffectual Computations of Bitmap Compressed Matrices (IEEE CAL) [paper]
  Chaithanya Krishna Vadlamudi, and Bahar Asgari

• Acamar: A Dynamically Reconfigurable Scientific Computing Accelerator for Robust Convergence and Minimal Resource Underutilization (MICRO) [paper]
  Ubaid Bakhtiar, Helia Hosseini, and Bahar Asgari

• Misam: Using ML in Dataflow Selection of Sparse-Sparse Matrix Multiplication (MLArchSys at ISCA) [paper]
  Sanjali Yadav, Bahar Asgari

• GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication (ASPLOS) [paper]
  Armin Gerami, Bahar Asgari

2023

• Memory-based computing for energy-efficient AI: Grand challenges (VLSI-SoC) [paper]
  Foroozan Karimzadeh, Mohsen Imani, Bahar Asgari, Ningyuan Cao, Yingyen Lin, and Yan Fang

• LCP: A Low-Communication Parallelization Method for Fast Neural Network Inference for IoT (CSCE-ICOMP) [paper] [slides]
  Ramyad Hadidi, Jiashen Cao, Younmin Bae, Da Eun Shim, Hyojong Kim, Bahar Asgari, Sung-Kyu Lim, Michael S. Ryoo, and Hyesoon Kim

• Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge (IEEE EDGE) [paper]
  Dheeraj Ramchandani, Bahar Asgari, and Hyesoon Kim

• Creating Robust Deep Neural Networks With Coded Distributed Computing for IoT (IEEE EDGE) [paper] [slides]
  Ramyad Hadidi, Jiashen Cao, Bahar Asgari, and Hyesoon Kim

• Context-Aware Task Handling in Resource-Constrained Robots with Virtualization (IEEE EDGE) [paper] [slides]
  Ramyad Hadidi, Nima Shoghi, Bahar Asgari, and Hyesoon Kim

2022

• Maia: Matrix Inversion Acceleration Near Memory (FPL) [paper]
  Bahar Asgari, Dheeraj Ramchandani, Amaan Marfatia, and Hyesoon Kim

2021

• Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads (IISWC) [paper]
  Bahar Asgari, Ramyad Hadidi, Joshua Dierberger, Charlotte Steinichen, Amaan Marfatia, Hyesoon Kim
  Best Paper Nominee!

• FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction (HPCA) [paper] [slides]
  Bahar Asgari, Ramyad Hadidi, Jiashen Cao, Da Eun Shim, Sung-Kyu Lim, Hyesoon Kim

• Quantifying the Design-Space Tradeoffs in Autonomous Drones (ASPLOS) [paper]
  Ramyad Hadidi, Bahar Asgari, Sam Jijina, Adriana Amyette, Nima Shoghi, Hyesoon Kim

• Context-Aware Task Handling in Resource-Constrained Robots with Virtualized Execution (DAC) [paper]
  Ramyad Hadidi, Bahar Asgari, Nima Shoghi, Hyesoon Kim

2020

• ALRESCHA: A Light-Weight Reconfigurable Sparse-Computation Accelerator (HPCA) [paper] [slides]
  Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili

• PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra (DAC) [paper] [slides]
  Bahar Asgari, Ramyad Hadidi, Nima Shoghi, Hyesoon Kim

• MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture (ICCD) [paper]
  Bahar Asgari, Ramyad Hadidi, Hyesoon Kim

• ASCELLA: Accelerating Sparse Problems by Enabling Stream Accesses to Memory (DATE) [paper] [slides]
  Bahar Asgari, Ramyad Hadidi, Hyesoon Kim

• Proposing a Fast and Scalable Systolic Array for Matrix Multiplication (FCCM) [paper] [slides]
  Bahar Asgari, Ramyad Hadidi, Hyesoon Kim

2019

• Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices (IISWC) [paper] [slides]
  Ramyad Hadidi, Jiashen Cao, Yilun Xie, Bahar Asgari, Tushar Krishna, Hyesoon Kim Best Paper Nominee!

• LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays (DAC) [paper]
  Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili

• SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM (DSN) [paper]
  Prashant Nair, Bahar Asgari, Moinuddin Qureshi

• Vortex RISC-V GPGPU system: Extending the ISA, Synthesizing the Microarchitecture, and Modeling the Software Stack (CARRV) [paper]
  Fares Elsabbagh, Bahar Asgari, Hyesoon Kim and Sudhakar Yalamanchili

• Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs (FPL) [paper] [slides]
  Younmin Bae, Ramyad Hadidi, Bahar Asgari, Jiashen Cao, Hyesoon Kim

• MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System [paper]
  Bahar Asgari, Saibal Mukhopadhyay, and Sudhakar Yalamanchili
  Springer Journal of Signal Processing Systems, Special Issue on Embedded Machine Learning (2020)

• ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays [paper]
  Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
  IEEE Micro, Special Issue on Machine Learning Acceleration (2019)

2018

• Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube (ISPASS) [paper] [slides]
  Ramyad Hadidi, Bahar Asgari, Jeffrey Young, Burhan Ahmad Mudassar, Kartikay Garg, Tushar Krishna, Hyesoon Kim

2017

• Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube (IISWC) [paper] [slides]
  Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, and Hyesoon Kim

2016

• A Micro-Architectural Approach to Efficient Employment of STTRAM Cells in Microprocessors Register File [paper]
  Bahar Asgari, Mahdi Fazeli, Ahmad Patooghy, and Seyed Vahid Azhari
  IET Computers and Digital Techniques (2016)

• Single Event Multiple Upset-Tolerant SRAM Cell Designs for Nano-scale CMOS Technology [paper]
  Ramin Rajaei, Bahar Asgari, Mahmoud Tabandeh, Mahdi Fazeli
  Turkish Journal of Electrical Engineering & Computer Sciences (2016)

2015

• Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies [paper]  
  Ramin Rajaei, Bahar Asgari, Mahmoud Tabandeh, and Mahdi Fazeli
  IEEE Transactions on Device and Materials Reliability (2015)